Conventionally, integrated circuit chips are interconnected using so-called two dimensional, or 2D, connections. For advanced devices, such as system on chip (SoC) devices having large layouts with numerous functional blocks (e.g., logic, I/O, memory, analog circuits, and the like) conventional 2D wiring has numerous limitations. These include I/O limitations because of the large number of interconnects and I/O ports required, power consumption/current leakage associated with 2D wiring, and high costs associated with the 2D wiring. These problems are exacerbated as technology nodes advance to the sub-micron scale, such as the 20 nanometer (N20) node and beyond. Conventional 2D wiring causes yield challenges as well, particularly for advanced node devices, such as field programmable gate arrays (FPGAs) and graphic processing units (GPUs).
So-called 3D wiring, which includes interconnecting multiple chips vertically as well as horizontally on a common substrate, is increasingly desirable for advanced devices. Silicon interposer packages may be employed to interconnect different integrated circuits, such as an advanced logic device and associated memory, such as a DRAM chip. The use of through silicon vias (TSVs) also aids more efficient packaging with 3D packages and allows for wider I/O connections. Such packages open the door for package on package (PoP) devices, such as a DRAM package stacked atop a Logic package. Despite the advantage, interposers introduce their own concerns, such as costs both in terms of the cost of the packaging as well as the size cost, particularly in profile sensitive applications such as mobile device applications. Power consumption of device packages limits higher system integration in mobile computing as well. Likewise, limitation on the I/O interconnect density limits higher system integration in mobile computing. Other challenges exist in packaging and particularly 3D packaging, as well, including the need for appropriate spacing for electrical connections, such as bumps and micro bumps.